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never stop thinking. hys64t32000[g/h]u?[3.7/5]?a hys[64/72]t64000[g/h]u?[3.7/5]?a hys[64/72]t128020[g/h]u?[3.7/5]?a 240-pin unbuffered ddr2 sdram modules ddr2 sdram data sheet, rev. 0.87, june 2004 memory products
the information in this document is subject to change without notice. edition 2004-06 published by infineon technologies ag, st.-martin-strasse 53, 81669 mnchen, germany ? infineon technologies ag 2004. all rights reserved. attention please! the information herein is given to describe certain comp onents and shall not be considered as a guarantee of characteristics. terms of delivery and rights to technical change reserved. we hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. information for further information on technology, delivery terms and conditions and prices please contact your nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements components may contain da ngerous substances. for information on the types in question please contact your near est infineon technologies office. infineon technologies components may only be used in life-support devices or systems with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. life support devices or systems are intended to be implanted in the hu man body, or to support and/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
never stop thinking. hys64t32000[g/h]u?[3.7/5]?a hys[64/72]t64000[g/h]u?[3.7/5]?a hys[64/72]t128020[g/h]u?[3.7/5]?a 240-pin unbuffered ddr2 sdram modules ddr2 sdram data sheet, rev. 0.87, june 2004 memory products
template: mp_a4_v2.3_2004-01-14.fm hys[64t[3200/6400/12802]0/72t[6400/12802]0][g/h]u?[3.7/5]?a revision history: rev. 0.87 2004-06 previous revision: rev. 0.84 2003-09 page subjects (major changes since last revision) all new template chapter 5 add currents all updated timings we listen to your comments any information within this document that yo u feel is wrong, unclear or missing at all? your feedback will help us to continuous ly improve the qualit y of this document. please send your proposal (including a reference to this document) to: techdoc.mp@infineon.com
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram data sheet 5 rev. 0.87, 2004-06 09122003-gzek-h4j6 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.1 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4 i dd specifications and conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.1 i dd test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.2 odt (on die termination) current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 5 electrical characteristics & ac timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 ac timing parameter by speed grade (component level data, for reference only) . . . . . . . . . . . . . 28 6 spd codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.1 raw card a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 7.2 raw card b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 7.3 raw card c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 8 product type nomenclature (ddr2 drams and dimms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table of contents
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 6 rev. 0.87, 2004-06 09122003-gzek-h4j6 1overview this chapter gives an overview of the 1.8 v 240-pin unbuffered ddr2 sdram modules, 256 mbyte, 512 mbyte & 1 gbyte ecc and non-ecc modules and describes its main characteristics. 1.1 features 240-pin ecc and non- ecc unbuffered 8-byte dual-in-line ddr2 sdram module for pc, workstation and server main memory applications one rank 32m x 64, 64m x 64, 64m x 72 and two ranks 128m 64 and 128m x 72 organization jedec standard double data rate 2 synchronous drams (ddr2 sdram) with a single + 1.8 v ( 0.1 v) power supply 256 ,512 mbyte and 1gbyte modules built with 512mb ddr2 sdrams in 60-ball (p?tfbga?60) and 84-ball fbga (p?tfbga?84) chipsize packages programmable cas latencies (3, 4 & 5), burst length (8 & 4) and burst type auto refresh (cbr) and self refresh all inputs and outputs sstl_1.8 compatible ocd (off-chip driver impedance adjustment) and odt (on-die termination) serial presence detect with e 2 prom low profile modules form factor: 133.35 mm x 30,00 mm (mo-237) based on jedec standard reference card layouts raw card ?a?, ?b? & ?c? 1.2 description the infineon hys[64/72]txxxx0[g/h]u module family are low profile un buffered dimm modules with 30,0 mm height based on ddr2 technology. dimms are available as non-ecc modules in 32m x 64 (256mb), 64m x 64 (512mb) and 128m x 64 (1024mb) and as ecc-modules in 64m x 72 (512mb) and 128m x 72 (1024mb) organisation and density, intended for mounting into 240 pin connector sockets. the memory array is designed with 512mb double data rate (ddr2) synchronous drams for ecc and non-ecc applications. de coupling capacitors are mounted on the pcb board. the dimms feature serial presence detect based on a serial e 2 prom device using the 2-pin i 2 c protocol. the first 128 bytes are programmed with configuration data and the second 128 bytes are available to the customer. table 1 performance speed grade indicator ?5 ?-3.7 unit component speed grade ddr2?400 ddr2?533 ? module speed grade pc2?3200 pc2?4200 ? max. clock frequency @ cl = 3 200 200 mhz max. clock frequency @ cl = 4 & 5 200 266 mhz
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 7 rev. 0.87, 2004-06 09122003-gzek-h4j6 note: 1. all part numbers end with a place code, designating the silicon die re vision. example: hys72t64000gu?5-a, indicating rev. a dice are used for ddr2 sdram components. for all infineon ddr2 module and component nomenclature see section 8 of this datasheet. 2. the compliance code is printed on the module label and describes the speed grade, f.e. ?pc2- 4200u-44410-c?, where 4200u means unbuffered dimm modules with 4.26 gb/sec module bandwidth and ?44410? means cas latency = 4, trcd latency = 4 and trp latency = 4 using the latest jedec spd revision 1.1 and produced on the raw card ?c?. table 2 ordering information product type compliance code description sdram technology pc2-3200 hys64t32000gu?5?a 256mb 1r 16 pc2?3200u?333?11?c0 1 rank, non-ecc 512 mbit ( 16) hys64t64000gu?5?a 512mb 1r 8 pc2?3200u?333?11?a0 1 rank, non-ecc 512 mbit ( 8) hys72t64000gu?5?a 512mb 1r 8 pc2?3200e?333?11?a0 1 rank, ecc 512 mbit ( 8) hys64t128020gu?5?a 1gb 2r 8 pc2?3200u?333?11?b0 2 ranks, non-ecc 512 mbit ( 8 hys72t128020gu?5?a 1gb 2r 8 pc2?3200e?333?11?b0 2 ranks, ecc 512 mbit ( 8) hys64t32000hu?5?a 256mb 1r 16 pc2?3200u?333?11?c0 1 rank, non-ecc 512 mbit ( 16) hys64t64000hu?5?a 512mb 1r 8 pc2?3200u?333?11?a0 1 rank, non-ecc 512 mbit ( 8) hys72t64000hu?5?a 512mb 1r 8 pc2?3200e?333?11?a0 1 rank, ecc 512 mbit ( 8) hys64t128020hu?5?a 1gb 2r 8 pc2?3200u?333?11?b0 2 ranks, non-ecc 512 mbit ( 8) hys72t128020hu?5?a 1gb 2r 8 pc2?3200e?333?11?b0 2 ranks, ecc 512 mbit ( 8) pc2?4200 hys64t32000gu?3.7?a 256mb 1r 16 pc2?4200u?444?11?c0 1 rank, non-ecc 512 mbit ( 16) hys64t64000gu?3.7?a 512mb 1r 8 pc2?4200u?444?11?a0 1 rank, non-ecc 512 mbit ( 8) hys72t64000gu?3.7?a 512mb 1r 8 pc2?4200e?444?11?a0 1 rank, ecc 512 mbit ( 8) hys64t128020gu?3.7?a 1gb 2r 8 pc2?4200u?444?11?b0 2 ranks, non-ecc 512 mbit ( 8 hys72t128020gu?3.7?a 1gb 2r 8 pc2?4200e?444?11?b0 2 ranks, ecc 512 mbit ( 8) hys64t32000hu?3.7?a 256mb 1r 16 pc2?4200u?444?11?c0 1 rank, non-ecc 512 mbit ( 16) hys72t64000hu?3.7?a 512mb 1r 8 pc2?4200e?444?11?a0 1 rank, ecc 512 mbit ( 8) hys64t64000hu?3.7?a 512mb 1r 8 pc2?4200u?444?11?a0 1 rank, non-ecc 512 mbit ( 8) hys64t128020hu?3.7?a 1gb 2r 8 pc2?4200u?444?11?b0 2 ranks, non-ecc 512 mbit ( 8) hys72t128020hu?3.7?a 1gb 2r 8 pc2?4200e?444?11?b0 2 ranks, ecc 512 mbit ( 8)
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 8 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 3 address format dimm density module organization memory ranks ecc/ non-ecc # of sdrams # of row/bank/columns bits raw card 256 mb 32m 64 1 non-ecc 4 13/2/10 c 512 mb 64m 64 1 non-ecc 8 14/2/10 a 512 mb 64m 72 1 ecc 9 14/2/10 a 1gb 2 64m 72 2 non-ecc 16 14/2/10 b 1gb 2 64m 72 2 ecc 18 14/2/10 b table 4 components on modules 1) 1) for a detailed description of all functionalities of the dra m components on these modules see the referenced component datasheet. part number dimm density dram components reference datasheet dram density dram organisation hys64t32000gu 256 mb hyb18t512160ac 512 mbit 32m 16 hys64t32000hu 2) 2) green product 256 mb hyb18t512160af 2) 512 mbit 32m 16 hys64t64000gu 512 mb hyb18t512800ac 512 mbit 64mb 8 hys64t64000hu 2) 512 mb hyb18t512800af 2) 512 mbit 64mb 8 hys72t64000gu 512 mb hyb18t512800ac 512 mbit 64mb 8 hys72t64000hu 2) 512 mb hyb18t512800af 2) 512 mbit 64mb 8 hys64t128020gu 1 gb hyb18t1g800ac 512 mbit 64mb 8 hys64t128020hu 2) 1 gb hyb18t1g800af 2) 512 mbit 64mb 8 hys72t128020gu 1 gb hyb18t1g800ac 512 mbit 64mb 8 hys72t128020hu 2) 1 gb hyb18t1g800af 2) 512 mbit 64mb 8
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 9 rev. 0.87, 2004-06 09122003-gzek-h4j6 1.3 pin configuration the pin configuration of the unbuffered ddr2 sdram dimm is listed by function in table 5 (240 pins). the abbreviations used in columns pin and buffer type are explained in table 6 and table 7 respectively. the pin numbering is depicted in figure 1 for non-ecc modules ( 64) and figure 2 for ecc modules ( 72). table 5 pin configuration of udimm pin# name pin type buffer type function clock signals 185 ck0 i sstl clock signals 2:0 137 ck1 i sstl 220 ck2 i sstl 186 ck0 i sstl complement clock signals 2:0 138 ck1 i sstl 221 ck2 i sstl 52 cke0 i sstl clock enable rank 0 171 cke1 i sstl clock enable rank 1 note: 2 ranks module nc nc ? note: 1 rank module control signals 193 s0 i sstl chip select rank 0 76 s1 i sstl chip select rank 1 note: 2 ranks module nc nc ? note: 1 rank module 192 ras i sstl row address strobe 74 cas i sstl column address strobe 73 we i sstl write enable address signals 71 ba0 i sstl bank address bus 1:0 190 ba1 i sstl 54 ba2 i sstl bank address bus 2 note: greater than 512mb ddr2 sdrams nc nc ? note: less than 1gb ddr2 sdrams 188 a0 i sstl address bus 12:0 183 a1 i sstl 63 a2 i sstl 182 a3 i sstl 61 a4 i sstl 60 a5 i sstl 180 a6 i sstl 58 a7 i sstl 179 a8 i sstl 177 a9 i sstl
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 10 rev. 0.87, 2004-06 09122003-gzek-h4j6 70 a10 i sstl address bus 12:0 ap i sstl 57 a11 i sstl 176 a12 i sstl 196 a13 i sstl address signal 13 note: 1 gbit based module and 512m 4/8 nc nc ? note: 1. module based on 1 gbit 16 2. module based on 512 mbit 16 or smaller 174 a14 i sstl address signal 14 note: modules based on 2 gbit nc nc ? note: modules based on 1 gbit or smaller data signals 3 dq0 i/o sstl data bus 63:0 4 dq1 i/o sstl 9 dq2 i/o sstl 10 dq3 i/o sstl 122 dq4 i/o sstl 123 dq5 i/o sstl 128 dq6 i/o sstl 129 dq7 i/o sstl 12 dq8 i/o sstl 13 dq9 i/o sstl 21 dq10 i/o sstl 22 dq11 i/o sstl 131 dq12 i/o sstl 132 dq13 i/o sstl 140 dq14 i/o sstl 141 dq15 i/o sstl 24 dq16 i/o sstl 25 dq17 i/o sstl 30 dq18 i/o sstl 31 dq19 i/o sstl 143 dq20 i/o sstl 144 dq21 i/o sstl 149 dq22 i/o sstl 150 dq23 i/o sstl 33 dq24 i/o sstl 34 dq25 i/o sstl table 5 pin configuration of udimm (cont?d) pin# name pin type buffer type function
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 11 rev. 0.87, 2004-06 09122003-gzek-h4j6 39 dq26 i/o sstl data bus 63:0 40 dq27 i/o sstl 152 dq28 i/o sstl 153 dq29 i/o sstl 158 dq30 i/o sstl 159 dq31 i/o sstl 80 dq32 i/o sstl 81 dq33 i/o sstl 86 dq34 i/o sstl 87 dq35 i/o sstl 199 dq36 i/o sstl 200 dq37 i/o sstl 205 dq38 i/o sstl 206 dq39 i/o sstl 89 dq40 i/o sstl 90 dq41 i/o sstl 95 dq42 i/o sstl 96 dq43 i/o sstl 208 dq44 i/o sstl 209 dq45 i/o sstl 214 dq46 i/o sstl 215 dq47 i/o sstl 98 dq48 i/o sstl 99 dq49 i/o sstl 107 dq50 i/o sstl 108 dq51 i/o sstl 217 dq52 i/o sstl 218 dq53 i/o sstl 226 dq54 i/o sstl 227 dq55 i/o sstl 110 dq56 i/o sstl 111 dq57 i/o sstl 116 dq58 i/o sstl 117 dq59 i/o sstl 229 dq60 i/o sstl 230 dq61 i/o sstl 235 dq62 i/o sstl 236 dq63 i/o sstl table 5 pin configuration of udimm (cont?d) pin# name pin type buffer type function
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 12 rev. 0.87, 2004-06 09122003-gzek-h4j6 check bit signal 42 cb0 i/o sstl check bit 0 note: ecc type module only nc nc ? note: non-ecc module 43 cb1 i/o sstl check bit 1 note: ecc type module only nc nc ? note: non-ecc module 48 cb2 i/o sstl check bit 2 note: ecc type module only nc nc ? note: non-ecc module 49 cb3 i/o sstl check bit 3 note: ecc type module only nc nc ? note: non-ecc module 161 cb4 i/o sstl check bit 4 note: ecc type module only nc nc ? note: non-ecc module 162 cb5 i/o sstl check bit 5 note: ecc type module only nc nc ? note: non-ecc module 167 cb6 i/o sstl check bit 6 note: ecc type module only nc nc ? note: non-ecc module 168 cb7 i/o sstl check bit 7 note: ecc type module only nc nc ? note: non-ecc module data strobe bus 7 dqs0 i/o sstl data strobe bus 8:0 note: see block diagram for corresponding dq signals 16 dqs1 i/o sstl 28 dqs2 i/o sstl 37 dqs3 i/o sstl 84 dqs4 i/o sstl 93 dqs5 i/o sstl 105 dqs6 i/o sstl 114 dqs7 i/o sstl 45 dqs8 i/o sstl 6dqs0 i/o sstl complement data strobe bus 8:0 note: see block diagram for corresponding dq signals 15 dqs1 i/o sstl 27 dqs2 i/o sstl 36 dqs3 i/o sstl 83 dqs4 i/o sstl table 5 pin configuration of udimm (cont?d) pin# name pin type buffer type function
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 13 rev. 0.87, 2004-06 09122003-gzek-h4j6 92 dqs5 i/o sstl complement data strobe bus 8:0 104 dqs6 i/o sstl 113 dqs7 i/o sstl 46 dqs8 i/o sstl data mask signals 125 dm0 i sstl data mask bus 8:0 134 dm1 i sstl 146 dm2 i sstl 155 dm3 i sstl 202 dm4 i sstl 211 dm5 i sstl 223 dm6 i sstl 232 dm7 i sstl 164 dm8 i sstl eeprom 120 scl i cmos serial bus clock 119 sda i/o od serial bus data 239 sa0 i cmos slave address select bus 2:0 240 sa1 i cmos 101 sa2 i cmos power supplies 1 v ref ai ? i/o reference voltage 238 v ddspd pwr ? eeprom power supply 51,56,62,72,75,78,170,175,181, 191,194 v ddq pwr ? i/o driver power supply 53,59,64,67,69,172,178,184,187 189,197 v dd pwr ? power supply 2,5,8,11,14,17,20,23,26,29,32, 35,38,41,44,47,50,65,66,79,82, 85,88,91,94,97,100,103,106, 109,112,115,118,121,124,127, 130,133,136,139,142,145,148, 151,154,157,160,163,166,169, 198,201,204,207,210,213,216, 219,222,225,228,231,234,237 v ss gnd ? ground plane other pins 195 odt0 on-die termination control 0 77 odt1 on-die termination control 1 note: 1 rank modules nc nc ? 18,19,55,68,102,126,135,147, 156,165,173,203,212, 224,233 nc nc ? not connected note: pins not connected on infineon udimms table 5 pin configuration of udimm (cont?d) pin# name pin type buffer type function
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 14 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 6 abbreviations for buffer type abbreviation description i standard input-only pin. digital levels. o output. digital levels. i/o i/o is a bidirectional input/output signal. ai input. analog levels. pwr power gnd ground nc not connected table 7 abbreviations for buffer type abbreviation description sstl serial stub terminated logic (sstl_18) lv-cmos low voltage cmos cmos cmos levels od open drain. the corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-or.
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 15 rev. 0.87, 2004-06 09122003-gzek-h4j6 figure 1 pin configuration udimm 64 (240 pin) mppt0150 pin 001 pin 003 pin 005 pin 007 pin 009 pin 011 pin 013 pin 015 pin 017 pin 019 - - - - - - - - - - pin 002 pin 004 pin 006 pin 008 pin 010 pin 012 pin 014 pin 016 pin 018 pin 020 - - - - - - - - - - vref dq0 v ss dqs0 dq2 v ss dq9 dqs1 v ss nc v ss dq1 dqs0 v ss dq3 dq8 v ss dqs1 nc v ss pin 022 pin 024 pin 026 pin 028 pin 030 pin 032 pin 034 pin 036 pin 038 pin 040 pin 042 pin 044 pin 046 pin 048 pin 050 pin 052 pin 054 pin 056 pin 058 pin 060 pin 062 pin 064 pin 066 pin 068 pin 070 pin 072 pin 074 pin 076 pin 078 pin 080 pin 082 pin 084 pin 086 pin 088 pin 090 pin 092 pin 094 pin 096 pin 098 pin 100 pin 102 pin 104 pin 106 pin 108 pin 110 pin 112 pin 114 pin 116 pin 118 pin 120 dq11 dq16 v ss dqs2 dq18 v ss dq25 dqs3 v ss dq27 nc v ss nc nc v ss cke0 nc/ba2 v ddq a7 a5 v ddq v dd v ss nc a10/ap v ddq cas nc/s1 v ddq dq32 v ss dqs4 dq34 v ss dq41 dqs5 v ss dq43 dq48 v ss nc dqs6 v ss dq51 dq56 v ss dqs7 dq58 v ss scl - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 021 pin 023 pin 025 pin 027 pin 029 pin 031 pin 033 pin 035 pin 037 pin 039 pin 041 pin 043 pin 045 pin 047 pin 049 pin 051 pin 053 pin 055 pin 057 pin 059 pin 061 pin 063 pin 065 pin 067 pin 069 pin 071 pin 073 pin 075 pin 077 pin 079 pin 081 pin 083 pin 085 pin 087 pin 089 pin 091 pin 093 pin 095 pin 097 pin 099 pin 101 pin 103 pin 105 pin 107 pin 109 pin 111 pin 113 pin 115 pin 117 pin 119 dq10 v ss dq17 dqs2 v ss dq19 dq24 v ss dqs3 dq26 v ss nc nc v ss nc v ddq v dd nc a11 v dd a4 a2 v ss v dd v dd ba0 we v ddq odt1 v ss dq33 dqs4 v ss dq35 dq40 v ss dqs5 dq42 v ss dq49 sa2 v ss dqs6 dq50 v ss dq57 dqs7 v ss dq59 sda - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 121 pin 123 pin 125 pin 127 pin 129 pin 131 pin 133 pin 135 pin 137 pin 139 - - - - - - - - - - pin 122 pin 124 pin 126 pin 128 pin 130 pin 132 pin 134 pin 136 pin 138 pin 140 - - - - - - - - - - v ss dq5 dm0 v ss dq7 dq12 v ss nc ck1 v ss dq4 v ss nc dq6 v ss dq13 dm1 v ss ck1 dq14 pin 142 pin 144 pin 146 pin 148 pin 150 pin 152 pin 154 pin 156 pin 158 pin 160 pin 162 pin 164 pin 166 pin 168 pin 170 pin 172 pin 174 pin 176 pin 178 pin 180 pin 182 pin 184 pin 186 pin 188 pin 190 pin 192 pin 194 pin 196 pin 198 pin 200 pin 202 pin 204 pin 206 pin 208 pin 210 pin 212 pin 214 pin 216 pin 218 pin 220 pin 222 pin 224 pin 226 pin 228 pin 230 pin 232 pin 234 pin 236 pin 238 pin 240 v ss dq21 dm2 v ss dq23 dq28 v ss nc dq30 v ss nc nc v ss nc v ddq v dd a14 a12 v dd a6 a3 v dd ck0 a0 ba1 ras v ddq nc/a13 v ss dq37 dm4 v ss dq39 dq44 v ss nc dq46 v ss dq53 ck2 v ss nc dq54 v ss dq61 dm7 v ss dq63 v ddspd sa1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 141 pin 143 pin 145 pin 147 pin 149 pin 151 pin 153 pin 155 pin 157 pin 159 pin 161 pin 163 pin 165 pin 167 pin 169 pin 171 pin 173 pin 175 pin 177 pin 179 pin 181 pin 183 pin 185 pin 187 pin 189 pin 191 pin 193 pin 195 pin 197 pin 199 pin 201 pin 203 pin 205 pin 207 pin 209 pin 211 pin 213 pin 215 pin 217 pin 219 pin 221 pin 223 pin 225 pin 227 pin 229 pin 231 pin 233 pin 235 pin 237 pin 239 dq15 dq20 v ss nc dq22 v ss dq29 dm3 v ss dq31 nc v ss nc nc v ss cke1 nc v ddq a9 a8 v ddq a1 ck0 v dd v dd v ddq s0 odt0 v dd dq36 v ss nc dq38 v ss dq45 dm5 v ss dq47 dq52 v ss ck2 dm6 v ss dq55 dq60 v ss nc dq62 v ss sa0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - frontside backside
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 16 rev. 0.87, 2004-06 09122003-gzek-h4j6 figure 2 pin configuration udimm 72 (240 pin) mppt0160 - - pin 001 pin 003 pin 005 pin 007 pin 009 pin 011 pin 013 pin 015 pin 017 pin 019 - - - - - - - - - - pin 002 pin 004 pin 006 pin 008 pin 010 pin 012 pin 014 pin 016 pin 018 pin 020 - - - - - - - - - - vref dq0 v ss dqs0 dq2 v ss dq9 dqs1 v ss nc v ss dq1 dqs0 v ss dq3 dq8 v ss dqs1 nc v ss pin 022 pin 024 pin 026 pin 028 pin 030 pin 032 pin 034 pin 036 pin 038 pin 040 pin 042 pin 044 pin 046 pin 048 pin 050 pin 052 pin 054 pin 056 pin 058 pin 060 pin 062 pin 064 pin 066 pin 068 pin 070 pin 072 pin 074 pin 076 pin 078 pin 080 pin 082 pin 084 pin 086 pin 088 pin 090 pin 092 pin 094 pin 096 pin 098 pin 100 pin 102 pin 104 pin 106 pin 108 pin 110 pin 112 pin 114 pin 116 pin 118 pin 120 dq11 dq16 v ss dqs2 v ss v ss dq25 dqs3 v ss dq27 cb0 v ss dqs8 cb2 v ss cke0 nc/ba2 v ddq a7 a5 v ddq v dd v ss nc a10/ap v ddq cas nc/s1 v ddq dq32 v ss dqs4 dq34 v ss dq41 dqs5 v ss dq43 dq48 v ss nc dqs6 v ss dq51 dq56 v ss dqs7 dq58 v ss scl - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 021 pin 023 pin 025 pin 027 pin 029 pin 031 pin 033 pin 035 pin 037 pin 039 pin 041 pin 043 pin 045 pin 047 pin 049 pin 051 pin 053 pin 055 pin 057 pin 059 pin 061 pin 063 pin 065 pin 067 pin 069 pin 071 pin 073 pin 075 pin 077 pin 079 pin 081 pin 083 pin 085 pin 087 pin 089 pin 091 pin 093 pin 095 pin 097 pin 099 pin 101 pin 103 pin 105 pin 107 pin 109 pin 111 pin 113 pin 115 pin 117 pin 119 dq10 v ss dq17 dqs2 v ss dq19 dq24 v ss dqs3 dq26 v ss cb1 dqs8 v ss cb3 v ddq v dd nc a11 v dd a4 a2 v ss v dd v dd ba0 we v ddq odt1 v ss dq33 dqs4 v ss dq35 dq40 v ss dqs5 v ss v ss dq49 sa2 v ss dqs6 dq50 v ss dq57 dqs7 v ss dq59 sda - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 121 pin 123 pin 125 pin 127 pin 129 pin 131 pin 133 pin 135 pin 137 pin 139 - - - - - - - - - - pin 122 pin 124 pin 126 pin 128 pin 130 pin 132 pin 134 pin 136 pin 138 pin 140 - - - - - - - - - - v ss dq5 dm0 v ss dq7 dq12 v ss nc ck1 v ss dq4 v ss nc dq6 v ss dq13 dm1 nc ck1 dq14 pin 142 pin 144 pin 146 pin 148 pin 150 pin 152 pin 154 pin 156 pin 158 pin 160 pin 162 pin 164 pin 166 pin 168 pin 170 pin 172 pin 174 pin 176 pin 178 pin 180 pin 182 pin 184 pin 186 pin 188 pin 190 pin 192 pin 194 pin 196 pin 198 pin 200 pin 202 pin 204 pin 206 pin 208 pin 210 pin 212 pin 214 pin 216 pin 218 pin 220 pin 222 pin 224 pin 226 pin 228 pin 230 pin 232 pin 234 pin 236 pin 238 pin 240 v ss dq21 dm2 v ss dq23 dq28 v ss nc dq30 v ss cb5 dm8 v ss cb7 v ddq v dd a14 a12 v dd a6 a3 v dd ck0 a0 ba1 ras v ddq nc/a13 v ss dq37 dm4 v ss dq39 dq44 v ss nc dq46 v ss dq53 ck2 v ss nc dq54 v ss dq61 dm7 v ss dq63 v ddspd sa1 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - pin 141 pin 143 pin 145 pin 147 pin 149 pin 151 pin 153 pin 155 pin 157 pin 159 pin 161 pin 163 pin 165 pin 167 pin 169 pin 171 pin 173 pin 175 pin 177 pin 179 pin 181 pin 183 pin 185 pin 187 pin 189 pin 191 pin 193 pin 195 pin 197 pin 199 pin 201 pin 203 pin 205 pin 207 pin 209 pin 211 pin 213 pin 215 pin 217 pin 219 pin 221 pin 223 pin 225 pin 227 pin 229 pin 231 pin 233 pin 235 pin 237 pin 239 dq15 dq20 v ss nc dq22 v ss dq29 dm3 v ss dq31 cb4 v ss nc cb6 v ss cke1 nc v ddq a9 a8 v ddq a1 ck0 v dd v dd v ddq s0 odt0 v dd dq36 v ss nc dq38 v ss dq45 dm5 v ss dq47 dq52 v ss ck2 dm6 v ss dq55 dq60 v ss nc dq62 v ss sa0 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - frontside backside
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram overview data sheet 17 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 8 input/output functional description symbol type polarity function ck0-ckn, ck 0-ckn i cross point the system clock inputs. all address and command lines are sampled on the cross point of the rising edge of ck and the falling edge of ck . a delay locked loop (dll) circuit is driven from the cl ock inputs and output timing for read operations is synchronized to the input clock. cke0- cken iactive high activates the ddr2 sdram ck signal when high and deactivates the ck signal when low. by deactivating the clocks, cke low initiates t he power down mode or the self refresh mode. s0 -sn iactive low enables the associated ddr2 sdram command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but pr evious operations continue. rank 0 is selected by s0 ; rank 1 is selected by s1 . ras , cas , we iactive low when sampled at the cross point of the rising edge of ck,and falling edge of ck , ras , cas and we define the operation to be executed by the sdram. ba0-ban i ? selects internal sdram memory bank odt0- odtn iactive high asserts on-die termination for dq, dm, dqs, and dqs signals if enabled via the ddr2 sdram mode register. a[9:0], a10/ap, a[12:11] i ? during a bank activate command cycle, defines the row address when sampled at the crosspoint of the rising edge of ck and falling edge of ck . during a read or write command cycle, defines the column address when sampled at the cross point of the rising edge of ck and falling edge of ck . in addition to the column address, ap is used to invoke autoprecharge operation at the end of the burst read or write cycle. if ap is high, au toprecharge is sele cted and ba0-ban defines the bank to be precharged. if ap is low, autoprecharge is disabled. during a precharge command cycle, ap is used in conjunction with ba[1:0] to control which bank(s) to precharge. if ap is high, all banks will be precharged regardless of the state of ba0-ban inputs. if ap is low, then ba0-ban are used to define which bank to precharge. dq[63:0] i/o ? data input/output pins dm[8:0] i active high the data write masks, associated with one data byte. in write mode, dm operates as a byte mask by a llowing input data to be writ ten if it is low but blocks the write operation if it is high. in read mode, dm lines have no effect . dqs[8:0], dqs [8:0] i/o cross point the data strobes, associated with one data byte, sourced with data transfers. in write mode, the data strobe is sourced by the controller and is centered in the data window. in read mode the data strobe is sourced by the ddr2 sdram and is sent at the leading edge of the data window. dqs signals are complements, and timing is relative to the crosspoint of respective dqs and dqs . if the module is to be operated in single ended strobe mode, all dqs signals must be tied on the system board to v ss through a 20 ohm to 10 kohm resistor and ddr2 sdram mode registers programmed appropriately. v dd , v ddspd , v ss supply ? power supplies for core, i/o, serial presence detect, and ground for the module. sda i/o ? this is a bidirectional pin used to transfer data into or out of the spd eeprom. a resistor must be connected from sda to to v ddspd on the motherboard to act as a pull-up. scl i ? this signal is used to clock da ta into and out of the spd eeprom. sa0-san i ? address pins used to select the serial presence detect base address.
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 18 rev. 0.87, 2004-06 09122003-gzek-h4j6 2blockdiagrams figure 3 block diagram raw card a udimm ( 64, 1 rank, 8) note 1. dq,dqs,dqs, dm resistors are 22 ? 5% 2. ban, an, ras , cas , we resistors are 5.1 ? 5% 3. odt,cke,s capacitors are 24 pf 4. all ck lines have resistor termination between ck an ck . table 9 clock signal loads clock input sdrams note ck0,cko 2 ck1,ck1 3 ck2,ck3 3
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 19 rev. 0.87, 2004-06 09122003-gzek-h4j6 figure 4 block diagram raw card a udimm ( 72, 1 rank, 8) note 1. dq,dqs,dqs, dm,cb resistors are 22 ? 5% 2. ban, an, ras , cas , we resistors are 5.1 ? 5% 3. odt,cke,s capacitors are 24 pf 4. all ck lines have resistor termination between ck an ck . table 10 clock signal loads clock input sdrams note ck0,ck0 3 1) 1) 2 sdrams for ck0 in case of non-ecc ck1,ck1 3 ck2,ck3 3
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 20 rev. 0.87, 2004-06 09122003-gzek-h4j6 ) figure 5 block diagram raw card b udimm ( 64, 1 rank, 8) note 1. dq,dqs,dqs, dm,cb resistors are 22 ? 5% 2. ban, an, ras , cas , we resistors are 7.5 ? 5% 3. odt,cke,s capacitors are 24 pf 4. all ck lines have resistor termination between ck an ck . mpbt0130 s0 d1 d2 d3 dm6 dqs6 dqs6 dq48 dq49 dq50 dq51 dq52 dq53 dq54 dq55 d6 dm7 dqs7 dqs7 dq56 dq57 dq58 dq59 dq60 dq61 dq62 dq63 d7 s1 d0 d8 d9 d10 d11 d4 d15 d14 d13 d5 d12 dm3 dqs3 dqs3 dq24 dq25 dq26 dq27 dq28 dq29 dq30 dq31 dm2 dqs2 dqs2 dq16 dq17 dq18 dq19 dq20 dq21 dq22 dq23 v ss scl sda sa0 sa1 v ss e0 scl sda a0 a1 a2 wp v dd : spd eeprom e0 v dd / v ddq : sdrams d0 - d15 v ref : sdrams d0 - d15 v ss : sdrams d0 - d15 v dd,spd v dd / v ddq v ref v ss ba0 - ba2: sdrams d0 - d15 a0 - an: sdrams d0 - d15 ras: sdrams d0 - d15 cas: sdrams d0 - d15 we: sdrams d0 - d15 cke 0: sdrams d0 - d7 cke 1: sdrams d8 - d15 odt 0: sdrams d0 - d7 odt 0: sdrams d8 - d15 ba0 - ba2 a0 - an ras cas we cke 0 cke 1 odt 0 odt 1 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm0 dqs0 dqs0 dq0 dq1 dq2 dq3 dq4 dq5 dq6 dq7 dm1 dqs1 dqs1 dq8 dq9 dq10 dq11 dq12 dq13 dq14 dq15 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm4 dqs4 dqs4 dq32 dq33 dq34 dq35 dq36 dq37 dq38 dq39 dm5 dqs5 dqs5 dq40 dq41 dq42 dq43 dq44 dq45 dq46 dq47 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 dm cs dqs dqs i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 table 11 clock signal loads clock input sdrams note ck0,ck0 4 ck1,ck1 6 ck2,ck3 6
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 21 rev. 0.87, 2004-06 09122003-gzek-h4j6 figure 6 block diagram raw card b udimm ( 72, 1 rank, 8) note: 1. dq,dqs,dqs, dm,cb resistors are 22 ? 5% 2. ban, an, ras , cas , we resistors are 7.5 ? 5% 3. odt,cke,s capacitors are 24 pf 4. all ck lines have resistor termination between ck an ck . table 12 clock signal loads clock input sdrams note ck0,ck0 6 ck1,ck1 6 ck2,ck3 6
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram block diagrams data sheet 22 rev. 0.87, 2004-06 09122003-gzek-h4j6 figure 7 block diagram raw card c udimm ( 64, 1rank, 16) note 1. dq, dqs, dm resistors are 22 ? 5% 2. ban, an, ras , cas , we resistors are 10 ? 5%
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics data sheet 23 rev. 0.87, 2004-06 09122003-gzek-h4j6 3 electrical characteristics 3.1 operating conditions note: stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional op eration of the device at these or any other conditions above those indicated in the operational sections of th is specification is not imp lied. exposure to absolute maximum rating conditions for exte nded periods may affect reliability. table 13 absolute maximum ratings parameter symbol limit values unit min. max. voltage on any pins relative to v ss v in , v out ? 0.5 2.3 v voltage on v dd relative to v ss v dd ? 1.0 2.3 v voltage on v dd q relative to v ss v ddq ? 0.5 2.3 storage temperature range t hstg -55 +100 c storage humidity (without condensation) h stg 595% table 14 operating conditions parameter symbol limit values unit notes min. max. dimm module operating temperature range (ambient) t opr 0+55 c dram component case temperature range t case 0+95 c 1)2)3)4) 1) dram component case temperature is the surface temperature in the center on the top side of any of the drams. for measurement conditions, please refer to the jedec document jesd51-2. 2) within the dram com ponent case temper ature range all dram specif ication will be supported. 3) above 85 c dram case temperature the auto-refresh command interval has to be reduced to t refi = 3.9 s. 4) self-refresh period is hard-coded in the drams and therefore it is im perative that the system ensures the dram is below 85 c case temperature before initiating self-refresh operation. barometric pressure (operating & storage) pbar +69 +105 kpa table 15 supply voltage levels and dc operating conditions parameter symbol limit values unit notes min. nom. max. device supply voltage v dd 1.7 1.8 1.9 v - output supply voltage v ddq 1.7 1.8 1.9 v 1) 1) under all conditions, v ddq must be less than or equal to v dd input reference voltage v ref 0.49 x v ddq 0.5 x v ddq 0.51 x v ddq v 2) 2) peak to peak ac noise on v ref may not exceed 2% v ref (dc). v ref is also expected to track noise variations in v ddq . eeprom supply voltage v ddspd 1.7 ? 3.6 v dc input logic high v ih (dc) v ref + 0.125 ? v ddq +0.3 v dc input logic low v il (dc) ? 0.30 ? v ref ? 0.125 v in / output leakage current i l ? 5 5 a 3) 3) voltage for pin connector under test input of 0 v v in v ddq + 0.3 v; all othe pins at 0 v. current is per pin
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 24 rev. 0.87, 2004-06 09122003-gzek-h4j6 4 i dd specifications and conditions table 16 i dd measurement conditions 1)2) parameter symbol operating current 0 one bank active - precharge; t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching . i dd0 operating current 1 one bank active - read - precharge; i out = 0 ma, bl = 4, t ck = t ckmin. , t rc = t rcmin ., t ras = t rasmin. , t rcd = t rcdmin. ,al = 0, cl = cl min .; cke is high, cs is high between valid commands. address and control inputs are switching, databus inputs are switching. i dd1 precharge power-down current other control and address inputs are stable, data bus inputs are floating . i dd2p precharge standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are switching, data bus inputs are switching. i dd2n precharge quiet standby current all banks idle; cs is high; cke is high; t ck = t ckmin. ; other control and address inputs are stable, data bus inputs are floating. i dd2q active power-down current all banks open; t ck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?0? (fast power-down exit); i dd3p(0) active power-down current all banks open; tck = t ckmin. , cke is low; other control and address inputs are stable, data bus inputs are floating. mrs a12 bit is set to ?1? (slow power-down exit); i dd3p(1) active standby current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin .; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd3n operating current burst read: all banks open; continuous burst reads; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i out = 0 ma. i dd4r operating current burst write: all banks open; continuous burst writes; bl = 4; al = 0, cl = cl min. ; t ck = t ckmin. ; t ras = t rasmax. , t rp = t rpmin. ; cke is high, cs is high between valid commands. address inputs are switching; data bus inputs are switching; i dd4w burst refresh current t ck = t ckmin ., refresh command every t rfc = t rfcmin. interval, cke is high, cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5b distributed refresh current t ck = t ckmin. , refresh command every t rfc = t refi interval, cke is low and cs is high between valid commands, other control and address inputs are switching, data bus inputs are switching. i dd5d
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 25 rev. 0.87, 2004-06 09122003-gzek-h4j6 self-refresh current cke 0.2 v; external clock off, ck and ck at 0 v; other control and address inputs are floating, data bus inputs are floating. reset = low. i dd6 current values are guaranteed up to t case of 85 c max. i dd6 all bank interleave read current all banks are being interleaved at minimum t rc without violating t rrd using a burst length of 4. control and address bus inputs are stable during deselects. i out = 0 ma. i dd7 1) v ddq = 1.8 v 0.1 v; v dd = 1.8 v 0.1 v 2) for details and notes see the relevant infineon component data sheet table 17 i dd specification product type hys64t32000gu-3.7-a hys64t32000hu-3.7-a hys64t64000gu-3.7-a hys64t64000hu-3.7-a hys72t64000gu-3.7-a hys72t64000hu-3.7-a hys64t128020gu-3.7-a hys64t128020hu-3.7-a hys72t128020gu-3.7-a hys72t128020hu-3.7-a unit notes organization 256mb 512mb 512mb 1gb 1gb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?3.7 ?3.7 ?3.7 ?3.7 ?3.7 symbol max. max. max. max. max. i dd0 320 520 585 552 621 ma 1) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled i dd1 360 600 675 632 711 ma 1) i dd2p 16 32 36 64 72 ma 1) i dd2f 160 320 360 640 720 ma 1) i dd2q 120 240 270 480 540 ma 1) i dd3p( mrs = 0) 64 128 144 256 288 ma 1) i dd3p( mrs = 1) 20 40 45 80 90 ma 1) i dd3n 160 320 360 640 720 ma 1) i dd4r 400 720 810 752 846 ma 1) i dd4w 440 760 855 792 891 ma 1) i dd5b 520 1040 1170 1072 1206 ma 1) i dd5d 24 48 54 96 108 ma 1) i dd6 16 32 36 64 72 ma 1) i dd7 880 1120 1260 1152 1296 ma 1) table 16 i dd measurement conditions 1)2) (cont?d) parameter symbol
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 26 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 18 i dd specification product type hys64t32000gu-5-a hys64t32000hu-5-a hys64t64000gu-5-a hys64t64000hu-5-a hys72t64000gu-5-a hys72t64000hu-5-a HYS64T128020GU-5-A hys64t128020hu-5-a hys72t128020gu-5-a hys72t128020hu-5-a unit notes organization 256mb 512mb 512mb 1gb 1gb 64 64 72 64 72 1 rank 1 rank 1 rank 2 ranks 2 ranks ?5 ?5 ?5 ?5 ?5 symbol max. max. max. max. max. i dd0 280 440 495 472 531 ma 1) 1) calculated values from component data. odt disabled. i dd1 , i dd4r and i dd7 are defined with the outputs disabled i dd1 300 480 540 512 576 ma 1) i dd2p 16 32 36 64 72 ma 1) i dd2f 128 256 288 512 576 ma 1) i dd2q 100 200 225 400 450 ma 1) i dd3p( mrs = 0) 52 104 117 208 234 ma 1) i dd3p( mrs = 1) 20 40 45 80 90 ma 1) i dd3n 140 280 315 560 630 ma 1) i dd4r 340 560 630 592 666 ma 1) i dd4w 360 600 675 632 711 ma 1) i dd5b 480 960 1080 992 1116 ma 1) i dd5d 24 48 54 96 108 ma 1) i dd6 16 32 36 64 72 ma 1) i dd7 840 1040 1170 1072 1206 ma 1)
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram i dd specifications and conditions data sheet 27 rev. 0.87, 2004-06 09122003-gzek-h4j6 4.1 i dd test conditions for testing the i dd parameters, the following timing parameters are used: 4.2 odt (on die termination) current the odt function adds additional current consumptio n to the ddr2 sdram when enabled by the emrs(1). depending on address bits a6 & a2 in the emrs(1) a ?week? or ?strong? termination can be selected. the current consumption for any terminated input pin, depends on the inpu t pin is in tristate or driving 0 or 1, as long a odt is enabled during a given period of time. note: for power consumption calculations the odt duty cycle has to be taken into account table 19 i dd measurement test conditions parameter symbol -5 -3.7 unit pc2-3200 pc2-4200 3-3-3 4-4-4 cas latency c lmin 34 t ck clock cycle time t ckmin 53.75ns active to read or write delay t rcdmin 15 15 ns active to active / auto-refresh command period t rcmin 55 60 ns active bank a to active bank b command delay x8 1) 1) for modules based on x8 components t rrdmin 7.5 7.5 ns x16 2) 2) for modules based on x16 components t rrdmin 10 10 ns active to precharge command t rasmin 40 45 ns precharge command period t rpmin 15 15 ns auto-refresh to active / auto-refresh command period t rfcmin 105 105 ns average periodic refresh interval t refi 7.8 7.8 s table 20 odt current per terminated pin: emrs(1) state min. typ. max. unit enabled odt current per dq added iddq current for odt enabled; odt is high; data bus inputs are floating i odto a6 = 0, a2 = 1 5 6 7.5 ma/dq a6 = 1, a2 = 0 2.5 3 3.75 ma/dq active odt current per dq added iddq current for odt enabled; odt is high; worst case of data bus inputs are stable or switching. i odtt a6 = 0, a2 = 1 10 12 15 ma/dq a6 = 1, a2 = 0 5 6 7.5 ma/dq
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 28 rev. 0.87, 2004-06 09122003-gzek-h4j6 5 electrical characteristics & ac timings 5.1 ac timing parameter by speed grade (component level data, for reference only) table 21 ac timing - absolute specifications ?5 / ?3.7 symbol parameter ?5 ?3.7 unit notes ddr2?400 ddr2?533 min. max. min. max. t ac dq output access time from ck/ck ? 600 + 600 -500 +500 ps 1) t ccd cas a to cas b command period 2 - 2 - t ck 1) t ch ck, ck high-level width 0.45 0.55 0.45 0.55 t ck 1) t ck clock cycle time 5000 8000 5000 8000 ps 1)2) 5000 8000 3750 8000 ps 1)3) t cke cke minimum high and low pulse width 3 - 3 - t ck 1) t cl ck, ck low-level width 0.45 0.55 0.45 0.55 t ck 1) t dal auto precharge write recovery + precharge time wr+ t rp -wr+ t rp - t ck 1) t delay minimum time clocks remain on after cke asynchronously drops low t is + t ck + t i h - t is + t ck + t ih -ns 1) t dh dq and dm input hold time 400 - 350 - ps 1)4) t dipw dq and dm input pulse width (each input) 0.35 - 0.35 - t ck 1) t dqsck dqs output access time from ck/ck ? 500 + 500 ? 450 + 450 ps 1) t dqsl,h dqs input low (high) pulse wi dth (write cycle) 0.35 - 0.35 - t ck 1) t dqss write command to 1st dqs latching transition wl - 0.25 wl +0.25 wl -0.25 wl +0.25 t ck 1) t dqsq dqs-dq skew (for dqs & associated dq signals) - 350 - 300 ps 1) t ds dq and dm input setup time 400 - 350 - ps 1)4) t dsh dqs falling edge hol d time from clk (write cycle) 0.2 - 0.2 - t ck 1) t dss dqs falling edge to clk setup time (write cycle) 0.2 - 0.2 - t ck 1) t hp clock half period min. (t cl, t ch) min. (t cl, t ch) 1) t hz data-out high-impedance time from ck/ck - t acmax - t acmax ps 1) t ih address and control input hold time 600 - 600 - ps 1)4) t ipw control and addr. input pulse width (each input) 0.6 - 0.6 - t ck 1) t is address and control input setup time 600 - 600 - ps 1)4) t lz(dq) dq low-impedance from ck / ck 2* t acmin t acmax 2* t acmin t acmax ps 1) t lz(dqs) dqs low-impedance from ck / ck t acmin t acmax t acmin t acmax ps 1) t mrd mode register set command cycle time 2 - 2 - t ck 1) t oit ocd drive mode output delay 0 12 0 12 ns 1) t ras active to precharge command 40 70000 45 70000 ns 1) t rc active to active/auto-refresh command period 55 - 60 - ns 1) t rcd active to read or write delay (with and without auto-precharge) delay 15 - 15 - ns 1)
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 29 rev. 0.87, 2004-06 09122003-gzek-h4j6 t refi average periodic refresh interval 0 c - 85 c - 7.8 - 7.8 s 1) 85 c - 95 c - 3.9 - 3.9 1) t rfc auto-refresh to active/auto-refresh command period 105 - 105 - ns 1) t rp precharge command period 15 - 15 - ns 1) t rpre read preamble 0.9 1.1 0.9 1.1 t ck 1) t rpst read postamble 0.40 0.60 0.40 0.60 t ck 1) t rrd active bank a to active bank b command x8 (1k page size) 7.5 - 7.5 - ns 1) x16 (2k page size) 10 - 10 - ns 1) t rtp internal read to precharge command delay 7.5 - 7.5 - ns 1) 1) t qh data output hold time from dqs t hp - t qhs -t hp -t qhs - 1) t qhs data hold skew factor - 450 - 400 ps 1) t wpre write preamble 0.25 - 0.25 - t ck 1) t wpst write postamble 0.40 0.60 0.40 0.60 t ck 1) t wr write recovery time 15 - 15 - ns 1) t wtr internal write to read command delay 10 - 7.5 - ns 1) t xard exit power down to any valid command (other than nop or deselect) 2-2- t ck 1) t xards exit active power-down mode to read command (slew exit, lower power) 6 - al - 6 - al - t ck 1) t xp exit precharge power-down to any valid command (other than nop or deselect) 2-2- t ck 1) t xsnr exit self-refresh to non-read command t rfc + 10 - t rfc + 10 -ns 1)5) t xsrd exit self-refresh to read command 200 - 200 - t ck 1)6) 1) for details and notes see the relevant infineon component datasheet 2) cl = 3 3) cl = 4 & 5 4) timing definition and values for t is , t ih , t ds and t dh may change due to actual jedec work. this may also effect the spd code for these parameters 5) 0c t case 85 c 6) 85 c < t case 95 c table 21 ac timing - absolute specifications ?5 / ?3.7 symbol parameter ?5 ?3.7 unit notes ddr2?400 ddr2?533 min. max. min. max.
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram electrical characteristics & ac timings data sheet 30 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 22 odt ac electrical characteristics and operating conditions (all speed bins) symbol parameter / condition min. max. unit t anpd odt to power down mode entry latency 3 - t ck t aof odt turn-off t ac (min) t ac (max) + 0.6 ns ns t aofd odt turn-off delay 2.5 2.5 t ck t aofpd odt turn-off delay (power-down modes) t ac (min) + 2 ns 2.5 t ck + t ac (max) + 1 ns ns t aon odt turn-on ddr2- 400/533 t ac (min) t ac (max) + 1 ns ns t aond odt turn-on delay 2 2 t ck t aonpd odt turn-on (power-down modes) t ac (min) + 2 ns 2 t ck + tac(max) + 1 ns ns t axpd odt power down exit latency 8 - t ck
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 31 rev. 0.87, 2004-06 09122003-gzek-h4j6 6spdcodes table 23 spd codes for hys[64/72]t[32/64]000gu?3.7?a product type hys64t32000gu?3.7?a hys64t64000gu?3.7?a hys72t64000gu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0e 0e 4 number of column addresses 0a 0a 0a 5 dimm rank and stacking information 60 60 60 6 data width 40 40 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 11 error correction support (non-ecc, ecc) 00 00 02 12 refresh rate and type 82 82 82 13 primary sdram width 10 08 08 14 error checking sdram width 00 00 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 not used 00 00 00 20 dimm type information 02 02 02 21 dimm attributes 00 00 00 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 32 rev. 0.87, 2004-06 09122003-gzek-h4j6 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 80 32 t as.min and t cs.min [ns] 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 22 22 22 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 00 00 00 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 45 t qhs.max [ns] 28 28 28 46 pll relock time 00 00 00 47 t case.max delta / ? t 4r4w delta 53 51 51 48 psi(t-a) dram 72 78 78 49 ? t 0 (dt0) 52 3e 3e 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2b 2e 2e 51 ? t 2p (dt2p) 1d 1e 1e 52 ? t 3n (dt3n) 1d 1e 1e 53 ? t 3p.fast (dt3p fast) 23 24 24 54 ? t 3p.slow (dt3p slow) 16 17 17 table 23 spd codes for hys[64/72]t[32/64]000gu?3.7?a (cont?d) product type hys64t32000gu?3.7?a hys64t64000gu?3.7?a hys72t64000gu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 33 rev. 0.87, 2004-06 09122003-gzek-h4j6 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 36 34 34 56 ? t 5b (dt5b) 1c 1e 1e 57 ? t 7 (dt7) 30 20 20 58 psi(ca) pll 00 00 00 59 psi(ca) reg 00 00 00 60 ? t pll (dtpll) 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 62 spd revision 11 11 11 63 checksum of bytes 0-62 b9 cf e1 64 jedec id code of infineon (1) c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 36 36 37 74 product type, char 2 34 34 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 79 product type, char 7 30 30 30 80 product type, char 8 30 30 30 81 product type, char 9 47 47 47 82 product type, char 10 55 55 55 83 product type, char 11 33 33 33 84 product type, char 12 2e 2e 2e 85 product type, char 13 37 37 37 86 product type, char 14 41 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 table 23 spd codes for hys[64/72]t[32/64]000gu?3.7?a (cont?d) product type hys64t32000gu?3.7?a hys64t64000gu?3.7?a hys72t64000gu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 34 rev. 0.87, 2004-06 09122003-gzek-h4j6 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 2x 2x 2x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 module serial number (1) xx xx xx 96 module serial number (2) xx xx xx 97 module serial number (3) xx xx xx 98 module serial number (4) xx xx xx 99 -127 not used 00 00 00 128- 255 blank ff ff ff table 23 spd codes for hys[64/72]t[32/64]000gu?3.7?a (cont?d) product type hys64t32000gu?3.7?a hys64t64000gu?3.7?a hys72t64000gu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 35 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 24 spd codes hys[64/72]t128020gu?3.7?a product type hys64t128020gu?3.7?a hys72t128020gu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e 4 number of column addresses 0a 0a 5 dimm rank and stacking information 61 61 6 data width 40 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 11 error correction support (non-ecc, ecc) 00 02 12 refresh rate and type 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 08 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 04 04 18 supported cas latencies 38 38 19 not used 00 00 20 dimm type information 02 02 21 dimm attributes 00 00 22 component attributes 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 36 rev. 0.87, 2004-06 09122003-gzek-h4j6 27 t rp.min [ns] 3c 3c 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 2d 2d 31 module density per rank 80 80 32 t as.min and t cs.min [ns] 25 25 33 t ah.min and t ch.min [ns] 37 37 34 t ds.min [ns] 10 10 35 t dh.min [ns] 22 22 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 1e 1e 38 t rtp.min [ns] 1e 1e 39 analysis characteristics 00 00 40 t rc and t rfc extension 00 00 41 t rc.min [ns] 3c 3c 42 t rfc.min [ns] 69 69 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 1e 1e 45 t qhs.max [ns] 28 28 46 pll relock time 00 00 47 t case.max delta / ? t 4r4w delta 51 51 48 psi(t-a) dram 78 78 49 ? t 0 (dt0) 3e 3e 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2e 2e 51 ? t 2p (dt2p) 1e 1e 52 ? t 3n (dt3n) 1e 1e 53 ? t 3p.fast (dt3p fast) 24 24 54 ? t 3p.slow (dt3p slow) 17 17 table 24 spd codes hys[64/72]t128020gu?3.7?a (cont?d) product type hys64t128020gu?3.7?a hys72t128020gu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 37 rev. 0.87, 2004-06 09122003-gzek-h4j6 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 34 34 56 ? t 5b (dt5b) 1e 1e 57 ? t 7 (dt7) 20 20 58 psi(ca) pll 00 00 59 psi(ca) reg 00 00 60 ? t pll (dtpll) 00 00 61 ? t reg (dtreg) / toggle rate 00 00 62 spd revision 11 11 63 checksum of bytes 0-62 d0 e2 64 jedec id code of infineon (1) c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 72 module manufacturer location xx xx 73 product type, char 1 36 37 74 product type, char 2 34 32 75 product type, char 3 54 54 76 product type, char 4 31 31 77 product type, char 5 32 32 78 product type, char 6 38 38 79 product type, char 7 30 30 80 product type, char 8 32 32 81 product type, char 9 30 30 82 product type, char 10 47 47 83 product type, char 11 55 55 84 product type, char 12 33 33 85 product type, char 13 2e 2e 86 product type, char 14 37 37 87 product type, char 15 41 41 88 product type, char 16 20 20 table 24 spd codes hys[64/72]t128020gu?3.7?a (cont?d) product type hys64t128020gu?3.7?a hys72t128020gu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 38 rev. 0.87, 2004-06 09122003-gzek-h4j6 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 2x 2x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 module serial number (1) xx xx 96 module serial number (2) xx xx 97 module serial number (3) xx xx 98 module serial number (4) xx xx 99 -127 not used 00 00 128-255 blank ff ff table 24 spd codes hys[64/72]t128020gu?3.7?a (cont?d) product type hys64t128020gu?3.7?a hys72t128020gu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 39 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 25 spd codes for hys[64/72]t[32/64]000hu?3.7?a product type hys64t32000hu?3.7?a hys64t64000hu?3.7?a hys72t64000hu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0e 0e 4 number of column addresses 0a 0a 0a 5 dimm rank and stacking information 60 60 60 6 data width 40 40 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 50 11 error correction support (non-ecc, ecc) 00 00 02 12 refresh rate and type 82 82 82 13 primary sdram width 10 08 08 14 error checking sdram width 00 00 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 not used 00 00 00 20 dimm type information 02 02 02 21 dimm attributes 00 00 00 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 40 rev. 0.87, 2004-06 09122003-gzek-h4j6 28 t rrd.min [ns] 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 80 32 t as.min and t cs.min [ns] 25 25 25 33 t ah.min and t ch.min [ns] 37 37 37 34 t ds.min [ns] 10 10 10 35 t dh.min [ns] 22 22 22 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 1e 1e 1e 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 00 00 00 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 1e 1e 1e 45 t qhs.max [ns] 28 28 28 46 pll relock time 00 00 00 47 t case.max delta / ? t 4r4w delta 53 51 51 48 psi(t-a) dram 72 78 78 49 ? t 0 (dt0) 52 3e 3e 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2b 2e 2e 51 ? t 2p (dt2p) 1d 1e 1e 52 ? t 3n (dt3n) 1d 1e 1e 53 ? t 3p.fast (dt3p fast) 23 24 24 54 ? t 3p.slow (dt3p slow) 16 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 36 34 34 table 25 spd codes for hys[64/72]t[32/64]000hu?3.7?a (cont?d) product type hys64t32000hu?3.7?a hys64t64000hu?3.7?a hys72t64000hu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 41 rev. 0.87, 2004-06 09122003-gzek-h4j6 56 ? t 5b (dt5b) 1c 1e 1e 57 ? t 7 (dt7) 30 20 20 58 psi(ca) pll 00 00 00 59 psi(ca) reg 00 00 00 60 ? t pll (dtpll) 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 62 spd revision 11 11 11 63 checksum of bytes 0-62 b9 cf e1 64 jedec id code of infineon (1) c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 36 36 37 74 product type, char 2 34 34 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 79 product type, char 7 30 30 30 80 product type, char 8 30 30 30 81 product type, char 9 48 48 48 82 product type, char 10 55 55 55 83 product type, char 11 33 33 33 84 product type, char 12 2e 2e 2e 85 product type, char 13 37 37 37 86 product type, char 14 41 41 41 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 table 25 spd codes for hys[64/72]t[32/64]000hu?3.7?a (cont?d) product type hys64t32000hu?3.7?a hys64t64000hu?3.7?a hys72t64000hu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 42 rev. 0.87, 2004-06 09122003-gzek-h4j6 90 product type, char 18 20 20 20 91 module revision code 2x 2x 2x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 module serial number (1) xx xx xx 96 module serial number (2) xx xx xx 97 module serial number (3) xx xx xx 98 module serial number (4) xx xx xx 99 -127 not used 00 00 00 128-255 blank ff ff ff table 25 spd codes for hys[64/72]t[32/64]000hu?3.7?a (cont?d) product type hys64t32000hu?3.7?a hys64t64000hu?3.7?a hys72t64000hu?3.7?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 43 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 26 spd codes for hys[64/72]t128020hu?3.7?a product type hys64t128020hu?3.7?a hys72t128020hu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e 4 number of column addresses 0a 0a 5 dimm rank and stacking information 61 61 6 data width 40 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 3d 3d 10 t ac sdram @ cl max (byte 18) [ns] 50 50 11 error correction support (non-ecc, ecc) 00 02 12 refresh rate and type 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 08 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 04 04 18 supported cas latencies 38 38 19 not used 00 00 20 dimm type information 02 02 21 dimm attributes 00 00 22 component attributes 01 01 23 t ck @ cl max -1 (byte 18) [ns] 3d 3d 24 t ac sdram @ cl max -1 [ns] 50 50 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 44 rev. 0.87, 2004-06 09122003-gzek-h4j6 27 t rp.min [ns] 3c 3c 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 2d 2d 31 module density per rank 80 80 32 t as.min and t cs.min [ns] 25 25 33 t ah.min and t ch.min [ns] 37 37 34 t ds.min [ns] 10 10 35 t dh.min [ns] 22 22 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 1e 1e 38 t rtp.min [ns] 1e 1e 39 analysis characteristics 00 00 40 t rc and t rfc extension 00 00 41 t rc.min [ns] 3c 3c 42 t rfc.min [ns] 69 69 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 1e 1e 45 t qhs.max [ns] 28 28 46 pll relock time 00 00 47 t case.max delta / ? t 4r4w delta 51 51 48 psi(t-a) dram 78 78 49 ? t 0 (dt0) 3e 3e 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 2e 2e 51 ? t 2p (dt2p) 1e 1e 52 ? t 3n (dt3n) 1e 1e 53 ? t 3p.fast (dt3p fast) 24 24 54 ? t 3p.slow (dt3p slow) 17 17 table 26 spd codes for hys[64/72]t128020hu?3.7?a (cont?d) product type hys64t128020hu?3.7?a hys72t128020hu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 45 rev. 0.87, 2004-06 09122003-gzek-h4j6 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 34 34 56 ? t 5b (dt5b) 1e 1e 57 ? t 7 (dt7) 20 20 58 psi(ca) pll 00 00 59 psi(ca) reg 00 00 60 ? t pll (dtpll) 00 00 61 ? t reg (dtreg) / toggle rate 00 00 62 spd revision 11 11 63 checksum of bytes 0-62 d0 e2 64 jedec id code of infineon (1) c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 72 module manufacturer location xx xx 73 product type, char 1 36 37 74 product type, char 2 34 32 75 product type, char 3 54 54 76 product type, char 4 31 31 77 product type, char 5 32 32 78 product type, char 6 38 38 79 product type, char 7 30 30 80 product type, char 8 32 32 81 product type, char 9 30 30 82 product type, char 10 48 48 83 product type, char 11 55 55 84 product type, char 12 33 33 85 product type, char 13 2e 2e 86 product type, char 14 37 37 87 product type, char 15 41 41 88 product type, char 16 20 20 table 26 spd codes for hys[64/72]t128020hu?3.7?a (cont?d) product type hys64t128020hu?3.7?a hys72t128020hu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 46 rev. 0.87, 2004-06 09122003-gzek-h4j6 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 2x 2x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 module serial number (1) xx xx 96 module serial number (2) xx xx 97 module serial number (3) xx xx 98 module serial number (4) xx xx 99 -127 not used 00 00 128-255 blank ff ff table 26 spd codes for hys[64/72]t128020hu?3.7?a (cont?d) product type hys64t128020hu?3.7?a hys72t128020hu?3.7?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?4200u?444 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 47 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 27 spd codes for hys[64/72]t32000gu?5?a product type hys64t32000gu?5?a hys64t64000gu?5?a hys72t64000gu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0e 0e 4 number of column addresses 0a 0a 0a 5 dimm rank and stacking information 60 60 60 6 data width 40 40 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 11 error correction support (non-ecc, ecc) 00 00 02 12 refresh rate and type 82 82 82 13 primary sdram width 10 08 08 14 error checking sdram width 00 00 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 not used 00 00 00 20 dimm type information 02 02 02 21 dimm attributes 00 00 00 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 48 rev. 0.87, 2004-06 09122003-gzek-h4j6 28 t rrd.min [ns] 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 80 32 t as.min and t cs.min [ns] 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 34 t ds.min [ns] 15 15 15 35 t dh.min [ns] 27 27 27 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 28 28 28 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 00 00 00 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 23 23 23 45 t qhs.max [ns] 2d 2d 2d 46 pll relock time 00 00 00 47 t case.max delta / ? t 4r4w delta 51 51 51 48 psi(t-a) dram 72 78 78 49 ? t 0 (dt0) 42 32 32 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 23 24 24 51 ? t 2p (dt2p) 1d 1e 1e 52 ? t 3n (dt3n) 19 1b 1b 53 ? t 3p.fast (dt3p fast) 1c 1e 1e 54 ? t 3p.slow (dt3p slow) 16 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 2e 28 28 56 ? t 5b (dt5b) 1a 1b 1b table 27 spd codes for hys[64/72]t32000gu?5?a (cont?d) product type hys64t32000gu?5?a hys64t64000gu?5?a hys72t64000gu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 49 rev. 0.87, 2004-06 09122003-gzek-h4j6 57 ? t 7 (dt7) 2d 1e 1e 58 psi(ca) pll 00 00 00 59 psi(ca) reg 00 00 00 60 ? t pll (dtpll) 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 62 spd revision 11 11 11 63 checksum of bytes 0-62 0b 23 35 64 jedec id code of infineon (1) c1 c1 c1 65 - 71 jedec id code of infineon (2- 8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 36 36 37 74 product type, char 2 34 34 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 79 product type, char 7 30 30 30 80 product type, char 8 30 30 30 81 product type, char 9 47 47 47 82 product type, char 10 55 55 55 83 product type, char 11 35 35 35 84 product type, char 12 41 41 41 85 product type, char 13 20 20 20 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 2x 2x 2x table 27 spd codes for hys[64/72]t32000gu?5?a (cont?d) product type hys64t32000gu?5?a hys64t64000gu?5?a hys72t64000gu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 50 rev. 0.87, 2004-06 09122003-gzek-h4j6 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 module serial number (1) xx xx xx 96 module serial number (2) xx xx xx 97 module serial number (3) xx xx xx 98 module serial number (4) xx xx xx 99 -127 not used 00 00 00 128-255 blank ff ff ff table 28 spd codes for hys[64/72]t128020gu?5?a product type hys64t128020gu?5?a hys72t128020gu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e table 27 spd codes for hys[64/72]t32000gu?5?a (cont?d) product type hys64t32000gu?5?a hys64t64000gu?5?a hys72t64000gu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 51 rev. 0.87, 2004-06 09122003-gzek-h4j6 4 number of column addresses 0a 0a 5 dimm rank and stacking information 61 61 6 data width 40 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 11 error correction support (non-ecc, ecc) 00 02 12 refresh rate and type 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 08 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 04 04 18 supported cas latencies 38 38 19 not used 00 00 20 dimm type information 02 02 21 dimm attributes 00 00 22 component attributes 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 27 t rp.min [ns] 3c 3c 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 2d 2d 31 module density per rank 80 80 table 28 spd codes for hys[64/72]t128020gu?5?a (cont?d) product type hys64t128020gu?5?a hys72t128020gu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 52 rev. 0.87, 2004-06 09122003-gzek-h4j6 32 t as.min and t cs.min [ns] 35 35 33 t ah.min and t ch.min [ns] 47 47 34 t ds.min [ns] 15 15 35 t dh.min [ns] 27 27 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 28 28 38 t rtp.min [ns] 1e 1e 39 analysis characteristics 00 00 40 t rc and t rfc extension 00 00 41 t rc.min [ns] 3c 3c 42 t rfc.min [ns] 69 69 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 23 23 45 t qhs.max [ns] 2d 2d 46 pll relock time 00 00 47 t case.max delta / ? t 4r4w delta 51 51 48 psi(t-a) dram 78 78 49 ? t 0 (dt0) 32 32 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 24 24 51 ? t 2p (dt2p) 1e 1e 52 ? t 3n (dt3n) 1b 1b 53 ? t 3p.fast (dt3p fast) 1e 1e 54 ? t 3p.slow (dt3p slow) 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 28 28 56 ? t 5b (dt5b) 1b 1b 57 ? t 7 (dt7) 1e 1e 58 psi(ca) pll 00 00 59 psi(ca) reg 00 00 table 28 spd codes for hys[64/72]t128020gu?5?a (cont?d) product type hys64t128020gu?5?a hys72t128020gu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 53 rev. 0.87, 2004-06 09122003-gzek-h4j6 60 ? t pll (dtpll) 00 00 61 ? t reg (dtreg) / toggle rate 00 00 62 spd revision 11 11 63 checksum of bytes 0-62 24 36 64 jedec id code of infineon (1) c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 72 module manufacturer location xx xx 73 product type, char 1 36 37 74 product type, char 2 34 32 75 product type, char 3 54 54 76 product type, char 4 31 31 77 product type, char 5 32 32 78 product type, char 6 38 38 79 product type, char 7 30 30 80 product type, char 8 32 32 81 product type, char 9 30 30 82 product type, char 10 47 47 83 product type, char 11 55 55 84 product type, char 12 35 35 85 product type, char 13 41 41 86 product type, char 14 20 20 87 product type, char 15 20 20 88 product type, char 16 20 20 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 2x 2x 92 test program revision code xx xx 93 module manufacturing date year xx xx table 28 spd codes for hys[64/72]t128020gu?5?a (cont?d) product type hys64t128020gu?5?a hys72t128020gu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 54 rev. 0.87, 2004-06 09122003-gzek-h4j6 94 module manufacturing date week xx xx 95 module serial number (1) xx xx 96 module serial number (2) xx xx 97 module serial number (3) xx xx 98 module serial number (4) xx xx 99 -127 not used 00 00 128-255 blank ff ff table 29 spd codes for hys[64/72]t[32/64]000hu?5?a product type hys64t32000hu?5?a hys64t64000hu?5?a hys72t64000hu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex 0 programmed spd bytes in eeprom 80 80 80 1 total number of bytes in eeprom 08 08 08 2 memory type (ddr2) 08 08 08 3 number of row addresses 0d 0e 0e 4 number of column addresses 0a 0a 0a 5 dimm rank and stacking information 60 60 60 table 28 spd codes for hys[64/72]t128020gu?5?a (cont?d) product type hys64t128020gu?5?a hys72t128020gu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 55 rev. 0.87, 2004-06 09122003-gzek-h4j6 6 data width 40 40 48 7 not used 00 00 00 8 interface voltage level 05 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 60 11 error correction support (non-ecc, ecc) 00 00 02 12 refresh rate and type 82 82 82 13 primary sdram width 10 08 08 14 error checking sdram width 00 00 08 15 not used 00 00 00 16 burst length supported 0c 0c 0c 17 number of banks on sdram device 04 04 04 18 supported cas latencies 38 38 38 19 not used 00 00 00 20 dimm type information 02 02 02 21 dimm attributes 00 00 00 22 component attributes 01 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 60 27 t rp.min [ns] 3c 3c 3c 28 t rrd.min [ns] 28 1e 1e 29 t rcd.min [ns] 3c 3c 3c 30 t ras.min [ns] 2d 2d 2d 31 module density per rank 40 80 80 32 t as.min and t cs.min [ns] 35 35 35 33 t ah.min and t ch.min [ns] 47 47 47 34 t ds.min [ns] 15 15 15 table 29 spd codes for hys[64/72]t[32/64]000hu?5?a (cont?d) product type hys64t32000hu?5?a hys64t64000hu?5?a hys72t64000hu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 56 rev. 0.87, 2004-06 09122003-gzek-h4j6 35 t dh.min [ns] 27 27 27 36 t wr.min [ns] 3c 3c 3c 37 t wtr.min [ns] 28 28 28 38 t rtp.min [ns] 1e 1e 1e 39 analysis characteristics 00 00 00 40 t rc and t rfc extension 00 00 00 41 t rc.min [ns] 3c 3c 3c 42 t rfc.min [ns] 69 69 69 43 t ck.max [ns] 80 80 80 44 t dqsq.max [ns] 23 23 23 45 t qhs.max [ns] 2d 2d 2d 46 pll relock time 00 00 00 47 t case.max delta / ? t 4r4w delta 51 51 51 48 psi(t-a) dram 72 78 78 49 ? t 0 (dt0) 42 32 32 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 23 24 24 51 ? t 2p (dt2p) 1d 1e 1e 52 ? t 3n (dt3n) 19 1b 1b 53 ? t 3p.fast (dt3p fast) 1c 1e 1e 54 ? t 3p.slow (dt3p slow) 16 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 2e 28 28 56 ? t 5b (dt5b) 1a 1b 1b 57 ? t 7 (dt7) 2d 1e 1e 58 psi(ca) pll 00 00 00 59 psi(ca) reg 00 00 00 60 ? t pll (dtpll) 00 00 00 61 ? t reg (dtreg) / toggle rate 00 00 00 62 spd revision 11 11 11 63 checksum of bytes 0-62 0b 23 35 table 29 spd codes for hys[64/72]t[32/64]000hu?5?a (cont?d) product type hys64t32000hu?5?a hys64t64000hu?5?a hys72t64000hu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 57 rev. 0.87, 2004-06 09122003-gzek-h4j6 64 jedec id code of infineon (1) c1 c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 00 72 module manufacturer location xx xx xx 73 product type, char 1 36 36 37 74 product type, char 2 34 34 32 75 product type, char 3 54 54 54 76 product type, char 4 33 36 36 77 product type, char 5 32 34 34 78 product type, char 6 30 30 30 79 product type, char 7 30 30 30 80 product type, char 8 30 30 30 81 product type, char 9 48 48 48 82 product type, char 10 55 55 55 83 product type, char 11 35 35 35 84 product type, char 12 41 41 41 85 product type, char 13 20 20 20 86 product type, char 14 20 20 20 87 product type, char 15 20 20 20 88 product type, char 16 20 20 20 89 product type, char 17 20 20 20 90 product type, char 18 20 20 20 91 module revision code 2x 2x 2x 92 test program revision code xx xx xx 93 module manufacturing date year xx xx xx 94 module manufacturing date week xx xx xx 95 module serial number (1) xx xx xx 96 module serial number (2) xx xx xx 97 module serial number (3) xx xx xx 98 module serial number (4) xx xx xx table 29 spd codes for hys[64/72]t[32/64]000hu?5?a (cont?d) product type hys64t32000hu?5?a hys64t64000hu?5?a hys72t64000hu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 58 rev. 0.87, 2004-06 09122003-gzek-h4j6 99 -127 not used 00 00 00 128-255 blank ff ff ff table 30 spd codes for hys[64/72]t128020hu?5?a product type hys64t128020hu?5?a hys72t128020hu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex 0 programmed spd bytes in eeprom 80 80 1 total number of bytes in eeprom 08 08 2 memory type (ddr2) 08 08 3 number of row addresses 0e 0e 4 number of column addresses 0a 0a 5 dimm rank and stacking information 61 61 6 data width 40 48 7 not used 00 00 8 interface voltage level 05 05 9 t ck @ cl max (byte 18) [ns] 50 50 10 t ac sdram @ cl max (byte 18) [ns] 60 60 table 29 spd codes for hys[64/72]t[32/64]000hu?5?a (cont?d) product type hys64t32000hu?5?a hys64t64000hu?5?a hys72t64000hu?5?a organization 256 mb 512 mb 512 mb 64 64 72 1 rank ( 16) 1 rank ( 8) 1 rank ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 rev. 1.1 byte# description hex hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 59 rev. 0.87, 2004-06 09122003-gzek-h4j6 11 error correction support (non-ecc, ecc) 00 02 12 refresh rate and type 82 82 13 primary sdram width 08 08 14 error checking sdram width 00 08 15 not used 00 00 16 burst length supported 0c 0c 17 number of banks on sdram device 04 04 18 supported cas latencies 38 38 19 not used 00 00 20 dimm type information 02 02 21 dimm attributes 00 00 22 component attributes 01 01 23 t ck @ cl max -1 (byte 18) [ns] 50 50 24 t ac sdram @ cl max -1 [ns] 60 60 25 t ck @ cl max -2 (byte 18) [ns] 50 50 26 t ac sdram @ cl max -2 [ns] 60 60 27 t rp.min [ns] 3c 3c 28 t rrd.min [ns] 1e 1e 29 t rcd.min [ns] 3c 3c 30 t ras.min [ns] 2d 2d 31 module density per rank 80 80 32 t as.min and t cs.min [ns] 35 35 33 t ah.min and t ch.min [ns] 47 47 34 t ds.min [ns] 15 15 35 t dh.min [ns] 27 27 36 t wr.min [ns] 3c 3c 37 t wtr.min [ns] 28 28 38 t rtp.min [ns] 1e 1e table 30 spd codes for hys[64/72]t128020hu?5?a (cont?d) product type hys64t128020hu?5?a hys72t128020hu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 60 rev. 0.87, 2004-06 09122003-gzek-h4j6 39 analysis characteristics 00 00 40 t rc and t rfc extension 00 00 41 t rc.min [ns] 3c 3c 42 t rfc.min [ns] 69 69 43 t ck.max [ns] 80 80 44 t dqsq.max [ns] 23 23 45 t qhs.max [ns] 2d 2d 46 pll relock time 00 00 47 t case.max delta / ? t 4r4w delta 51 51 48 psi(t-a) dram 78 78 49 ? t 0 (dt0) 32 32 50 ? t 2n (dt2n, udimm) or ? t 2q ( (dt2q, rdimm) 24 24 51 ? t 2p (dt2p) 1e 1e 52 ? t 3n (dt3n) 1b 1b 53 ? t 3p.fast (dt3p fast) 1e 1e 54 ? t 3p.slow (dt3p slow) 17 17 55 ? t 4r (dt4r) / ? t 4r4w s sign (dt4r4w) 28 28 56 ? t 5b (dt5b) 1b 1b 57 ? t 7 (dt7) 1e 1e 58 psi(ca) pll 00 00 59 psi(ca) reg 00 00 60 ? t pll (dtpll) 00 00 61 ? t reg (dtreg) / toggle rate 00 00 62 spd revision 11 11 63 checksum of bytes 0-62 24 36 64 jedec id code of infineon (1) c1 c1 65 - 71 jedec id code of infineon (2 - 8) 00 00 72 module manufacturer location xx xx table 30 spd codes for hys[64/72]t128020hu?5?a (cont?d) product type hys64t128020hu?5?a hys72t128020hu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram spd codes data sheet 61 rev. 0.87, 2004-06 09122003-gzek-h4j6 73 product type, char 1 36 37 74 product type, char 2 34 32 75 product type, char 3 54 54 76 product type, char 4 31 31 77 product type, char 5 32 32 78 product type, char 6 38 38 79 product type, char 7 30 30 80 product type, char 8 32 32 81 product type, char 9 30 30 82 product type, char 10 48 48 83 product type, char 11 55 55 84 product type, char 12 35 35 85 product type, char 13 41 41 86 product type, char 14 20 20 87 product type, char 15 20 20 88 product type, char 16 20 20 89 product type, char 17 20 20 90 product type, char 18 20 20 91 module revision code 2x 2x 92 test program revision code xx xx 93 module manufacturing date year xx xx 94 module manufacturing date week xx xx 95 module serial number (1) xx xx 96 module serial number (2) xx xx 97 module serial number (3) xx xx 98 module serial number (4) xx xx 99 -127 not used 00 00 128-255 blank ff ff table 30 spd codes for hys[64/72]t128020hu?5?a (cont?d) product type hys64t128020hu?5?a hys72t128020hu?5?a organization 1 gbyte 1 gbyte 64 72 2 ranks ( 8) 2 ranks ( 8) label code pc2?3200u?333 jedec spd revision rev. 1.1 rev. 1.1 byte# description hex hex
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 62 rev. 0.87, 2004-06 09122003-gzek-h4j6 7 package outlines 7.1 raw card a figure 8 package outline l-dim-240-1 gld09652 c b a 0.1 4 133.35 b 30 0.1 128.95 120 1 0.1 4 2.5 0.1 5 0.1 0.1 63 2.7 max. 1.27 c 0.3 0.1 0.1 55 0.1 1.5 a 240 2.3 0.1 0.1 10 0.1 17.8 3.8 121 3 min. burr max. 0.4 allowed 0.2 1 detail of contacts c 0.2 0.8 0.1 a b 2.5 0.2
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 63 rev. 0.87, 2004-06 09122003-gzek-h4j6 7.2 raw card b figure 9 package outline l-dim-240-2 gld09653 c b a 0.1 4 133.35 b 30 0.1 128.95 120 1 0.1 4 2.5 0.1 5 0.1 0.1 63 4 max. 1.27 c 0.4 0.1 0.1 55 0.1 1.5 a 240 2.3 0.1 0.1 10 0.1 17.8 3.8 121 3 min. burr max. 0.4 allowed 0.2 1 detail of contacts c 0.2 0.8 0.1 a b 2.5 0.2
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram package outlines data sheet 64 rev. 0.87, 2004-06 09122003-gzek-h4j6 7.3 raw card c figure 10 package outline l-dim-240-3 gld09654 1 128.95 133.35 4 0.1 bc a 1.27 0.4 c 0.1 2.7 max. 30 120 2.5 4 5 63 b 55 0.1 1.5 3.8 121 240 10 17.8 (3) burr max. 0.4 allowed 2.5 0.2 0.05 0.8 0.1 a bc detail of contacts 0.2 a 1 0.1 2.3 4x
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram product type nomenclature (ddr2 drams and dimms) data sheet 65 rev. 0.87, 2004-06 09122003-gzek-h4j6 8 product type nomenclature (ddr2 drams and dimms) infineon?s nomenclature uses simple coding combined with some propriatory coding. table 31 provides examples for module and component product type number as well as the field number. the detailed field description together with possible values and coding explanation is listed for modules in table 32 and for components in table 33 . table 31 nomenclature fields and examples example for field number 1234567891011 micro-dimm hys 64 t 64 0 2 0 k m ?5 ?a ddr2 dram hyb 18 t 512 16 0 a c ?5 table 32 ddr2 dimm nomenclature field description values coding 1 infineon modul prefix hys constant 2 module data width [bit] 64 non-ecc 72 ecc 3 dram technology t ddr2 4 memory density per i/o [mbit]; module density 1) 1) multiplying ?memory density per i/o? with ?module data wi dth? and dividing by 8 for non-ecc and 9 for ecc modules gives the overall module memory density in mbytes as listed in column ?coding?. 32 256 mbyte 64 512 mbyte 128 1 gbyte 256 2 gbyte 5 raw card generation 0 .. 9 look up table 6 number of module ranks 0, 2, 4 1, 2, 4 7 product variations 0 .. 9 look up table 8 package, lead-free status a .. z look up table 9 module type s s o-dimm m m icro-dimm r r egistered u u nbuffered 10 speed grade ?3.7 pc2?4200 4?4?4 ?5 pc2?3200 3?3?3 11 die revision ?a first ?b second
hys[64t[3200/6400/12802]0 /72t[6400/12802]0][g/h]u?[3.7/5]?a 512 mbit ddr2 sdram product type nomenclature (ddr2 drams and dimms) data sheet 66 rev. 0.87, 2004-06 09122003-gzek-h4j6 table 33 ddr2 dram nomenclature field description values coding 1infineon component prefix hyb constant 2 interface voltage [v] 18 sstl1.8 3 dram technology t ddr2 4 component density [mbit] 256 256 mbit 512 512 mbit 1g 1 gbit 2g 2 gbit 5+6 number of i/os 40 4 80 8 16 16 7 product variations 0 .. 9 look up table 8 die revision a first b second 9 package, lead-free status c fbga, lead-containing f fbga, lead-free 10 speed grade ?3.7 ddr2-533 ?5 ddr2-400 11 n/a for components
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